1. Field of the Invention
The present invention relates to a data transfer system and to a data transfer apparatus. More specifically, the invention relates to a data transfer system used for a computer and, particularly, for a parallel computer, a computer graphic (CG) accelerator or an image processing accelerator, and to a data transfer apparatus used therefor.
2. Description of the Related Art
So far, many operation methods have been developed and put into practical use for moving large amounts of data at high speeds in computers. In computers, computer graphics and image processing systems require the transfer of a predetermined amount of data at high speeds among a plurality of apparatuses (masters) by using a parallel processing system. For this purpose, an operation processing circuit must be developed.
FIG. 20 is a block diagram illustrating the constitution of a traditional data transfer apparatus that is used for transferring data at high speeds in high-speed processing.
That is, in the conventional data transfer apparatus shown in FIG. 20, a plurality of masters 1A, 1B and 1C are connected to corresponding data-holding means (data buffer means) 3A, 3B and 3C via data buses 2A, 2B and 2C, and outputs 4A, 4B and 4C of the data buffer means 3A, 3B and 3C are connected to a common I/O terminal 6 of a shared memory 5 via a memory data bus 4.
Here, the master generally stands for an operation processing constitution which at least includes a host computer, has a function for operating on the data, has a function for inputting data, stores the results of an operation processed by the operation function, and further has an output function (the word master is hereinafter used to designate the same object).
In the conventional data transfer apparatus of this system, predetermined data are transferred between a memory (shared memory) and a plurality (n) of masters. The above system has been so constituted that the predetermined data are transferred not only between a given master 1N and the shared memory 5 but also between one master and another master in the plurality of the masters 1A to 1N.
In the above conventional data transfer apparatus, when it is desired to transfer predetermined data from a master 1A to another master such as 1B, the predetermined data output from the master 1A is once written and stored in a predetermined address in the shared memory 5 that is connected to the memory data bus 4 via the data buffer means 3A and, then, the master 1B, to which the data should be transferred, makes an access to the shared memory 5 to read the address thereof.
In this constitution, the data can be transferred most quickly when no access is made from other masters while the master 1A is writing the data to be transferred into the shared memory 5 and the master 1B is reading the data from the shared memory. The transfer of data, however, needs a predetermined cyclic period i.
In the above constitution, however, when an access is made from other masters, contention of data occurs on the memory data bus and a considerable number of cycles are needed before the predetermined data is transferred, and the transfer speed of the data to be operated is reduced correspondingly.
FIG. 21 is a timing chart for transferring the data by the conventional data transfer apparatus shown in FIG. 20, wherein FIG. 21(A) explains the case where the data is to be transferred from the master 1A to the master 1B.
FIG. 21(A) is a timing chart explaining the case where the master 1A makes access to the shared memory 5 to write data therein in order to transfer the predetermined data from the master 1A to the master 1B and where no access is being made to the shared memory from a master 1N other than the master 1B before the master 1B outputs an access signal for requesting the reading, and FIG. 21(B) is a timing chart explaining the case where the master 1A makes access to the shared memory 5 to write data therein in order to transfer the predetermined data from the master 1A to the master 1B and where an access is made to the shared memory from a master 1N other than the master 1B before the master 1B outputs an access signal for requesting the reading.
That is, FIG. 21(A) is a timing chart of the case where the data are transferred from the master 1A to the master 1B, wherein an address data strobe signal A-ADS is, first, output in response to a clock signal t2, an address data is output to write the data of the master A onto a predetermined position of the shared memory 5, an A-DTACK signal is turned on to indicate that the data is ready to be written into the shared memory 5 and, then, the master A is allowed to execute another operational processing.
A write enable signal (DRAM-WE) to the shared memory 5 is turned on in response to a clock signal t4 and, as a result, an address DRAM-RAS in the DRAM of the shared memory 5 is turned on, so that the data from the master 1A is written into the memory.
On the other hand, the master 1B that receives the predetermined data from the master 1A outputs an address data strobe signal B-ADS in response to a clock signal t3, outputs an address data to write the data into a predetermined position of the shared memory 5, and wherein a B-DTACK signal is turned on in response to a clock signal t9 to indicate that the data is ready to be written into the shared memory 5. The master 1B is then allowed to execute another operation processing.
For this purpose, a write enable signal is output at a suitable timing or, in this example, at around a clock signal t8 to read the data.
FIG. 21(B) illustrates an example where the data to be transferred is output from the master 1A to the shared memory 5, and address signals C-ADS and D-ADS related to other data are output from other masters 1C and 1D before the master 1B outputs the address signal B-ADS for designating the address of the shared memory 5 to read the data that is to be transferred. The address signal C-ADS related to other data is output from the master 1C in response to a clock signal t5 and, hence, the data of the master 1C is written into the address DRAM-RAS in the DRAM of the shared memory 5.
Similarly, data corresponding to D-ADS from the master 1D is written into the DRAM of the shared memory.
After the above interrupt processing is finished, the B-DTACK signal is produced for the first time in response to a clock signal t18.
That is, in this example, an interrupt generated by another master causes a great delay before the data from the master 1A is read by the master 1B.
In the conventional data transfer apparatus, therefore, each of the plurality of masters had to make access to the single shared memory. Once contention of data occurred in the memory data bus, therefore, a considerable period of time was needed before the transfer of data was finished. Therefore, it has became necessary to develop a new data transfer apparatus.
According to a method of solving the above-mentioned problem as indicated by a dotted line in FIG. 20, provision is made of data buffer means 7-1 and 7-2 directly connecting the data buses of the two different masters in order to realize the transfer of data between the two masters without using the shared memory 5.
According to the above constitution, the data are transferred without passing through the shared memory 5 unlike the aforementioned prior art, and the data can be transferred very quickly. However, data buffer means are necessary for transferring the data among the masters in addition to data buffer means between the masters and the memory, resulting in a complex circuit constitution and lengthened wirings. It is therefore difficult to realize the apparatus in a small size without increasing the cost.